Error correcting code (“ECC”) schemes are widely used in large memory arrays to detect and/or correct errors in the memory array due to imperfections such as manufacturing defects, design marginalities, or loss of data due to alpha particle collisions. In conventional ECC schemes, syndrome bits are generated at the time data bits are stored in the memory array, and these bits are stored along with the data bits as an ECC word. When read back from the memory array, the ECC scheme evaluates the data and syndrome bits to check the integrity of the ECC word. Commonly-used ECC schemes can detect multi-bit errors and correct single-bit errors. Typically, the bits of the ECC word are stored in close physical proximity in the memory array to simplify the physical design of the memory circuits. With commonly-used ECC schemes, if a local defect impacts only a single-bit location, the error will be corrected. However, some manufacturing defects affect multiple bits in close proximity to one another. If the defect hits several bit locations in an ECC word, commonly-used ECC schemes will not be able to correct the resulting multi-bit errors, and the data in the ECC word will be lost. This problem results in reduced yield and/or reliability of the memory device.
There is a need, therefore, for a method for storing bits in non-adjacent storage locations in a memory array that can be used to improve yield and reliability in memory devices that use error detection and/or correction schemes.